1. Field of the Invention
The invention relates to a communication system for inter-chip communication in which processors communicate with one another via data channels of a communication bus, wherein a processor designated as a master processor assumes control of the transmission to the other processor designated as a slave processor.
2. Related Art
In this context, a bus system is already known for synchronous serial data transmission according to the master-slave principle, which is also referred to as a serial peripheral interface (SPI for short). This bus system has three common lines to which each participant is connected. These lines are an output for serial data, an input for serial data and a timer control (clock), which is defined by the master controlling the communication. A transmit enable line is furthermore provided between the master controlling the communication and the slave. The communication between the master and slave is effected bidirectionally and, according to the implementation of the protocol, is full-duplex-enabled. This requires many settings between the master and slave. The data protocols that enable the data flow and the data analysis on both sides of the communication partners are accordingly highly complex due to the bidirectional data transmission. The bidirectional data transmission can also result in an excessively high system load, particularly because the master and slave are able to, and must, transmit, receive and process data in parallel.
A substantial problem with this SPI bus consists in that the beginning of a message in the data flow is not known and may essentially start with any data bit.
Due to the complex protocol structure and the hardware-dependent implementation of the communication, proprietary communication solutions are often used for many processors, rendering an interoperability of different communication partners consisting of different hardware more or less impossible. The implementation of the SPI bus therefore always depends on the processors involved.
The problem with SPI inter-chip communication is therefore that both the SPI master controlling the communication flow and the SPI slave must be able to transmit, receive and process the data in parallel. This is a problem above all for the SPI slave, since it must always be ready to receive because the data transmission by the SPI master may, in principle, start at any time, i.e., with any bit. Even in the case of a data transmission by the SPI slave, the transmission flow is controlled by the SPI master. Consequently, the SPI slave must guarantee a continuous data flow in its data transmit register (controlled by the SPI master) as long as the data transmission from the SPI slave to the SPI master takes place. The protocols necessary for this purpose are complex and result in a high system load on the bus for inter-chip communication.
Furthermore, the implementation of the known SPI bus for inter-chip communication is strongly system-dependent, since there are many possible settings for the SPI bus. The reason for this is that the specifications for an SPI bus are not precisely defined and therefore many different, even mutually incompatible, devices exist. It may thus occur that a dedicated configuration of the SPI master is required for each connected circuit. The reason for this is, for example, that there is no uniform control for the communication direction or the communication of different participants. If a plurality of participants communicate simultaneously on one data channel, collisions frequently occur.